Difference between revisions of "Escaped identifiers in RTL files and in Verific data structures"
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'''Verific Data Structures :''' | '''Verific Data Structures :''' | ||
| − | + | In Verific Data Structures (parsetrees and netlist database) there are no naming rules, hence no need to escape identifiers. | |
| − | In netlist outputs and in pretty-print outputs, | + | In netlist outputs and in pretty-print outputs, naming rules are applied to identifiers based on the naming rules of the language of the output file. As a result, identifiers in the output file may need to be escaped. |
| − | '''Verilog :''' | + | '''For Verilog :''' |
Escaped identifiers begin with a backslash and end with a space character. | Escaped identifiers begin with a backslash and end with a space character. | ||
| − | + | Per the LRMs, the escaping characters '\' and ' ' are not part of the name : 'foo' is the same object as '\foo '. | |
When using AddSignal() to create a new signal, the specified name does not need to be escaped. | When using AddSignal() to create a new signal, the specified name does not need to be escaped. | ||
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When referring to an escaped identifier, the name must be escaped. | When referring to an escaped identifier, the name must be escaped. | ||
| − | To get the 'Verilog name' for an identifier in the Verilog parsetree use VeriNode::MakeVerilogName() | + | To get the 'Verilog name' for an identifier in the Verilog parsetree, use VeriNode::MakeVerilogName() |
| − | To get the 'Verilog name' for an identifier in the netlist database use VeriWrite::MakeVerilogName() | + | To get the 'Verilog name' for an identifier in the netlist database, use VeriWrite::MakeVerilogName() |
| − | '''VHDL :''' | + | '''For VHDL :''' |
Escaped identifiers are enclosed in a pair of backslashes. | Escaped identifiers are enclosed in a pair of backslashes. | ||
| − | + | Per the LRMs, the backslashes are part of the name : '\foo\' and 'foo' are two different objects, and thus both are stored in the parsetree as different nodes. | |
Latest revision as of 08:51, 16 June 2023
Verific Data Structures :
In Verific Data Structures (parsetrees and netlist database) there are no naming rules, hence no need to escape identifiers.
In netlist outputs and in pretty-print outputs, naming rules are applied to identifiers based on the naming rules of the language of the output file. As a result, identifiers in the output file may need to be escaped.
For Verilog :
Escaped identifiers begin with a backslash and end with a space character.
Per the LRMs, the escaping characters '\' and ' ' are not part of the name : 'foo' is the same object as '\foo '.
When using AddSignal() to create a new signal, the specified name does not need to be escaped.
When referring to an escaped identifier, the name must be escaped.
To get the 'Verilog name' for an identifier in the Verilog parsetree, use VeriNode::MakeVerilogName()
To get the 'Verilog name' for an identifier in the netlist database, use VeriWrite::MakeVerilogName()
For VHDL :
Escaped identifiers are enclosed in a pair of backslashes.
Per the LRMs, the backslashes are part of the name : '\foo\' and 'foo' are two different objects, and thus both are stored in the parsetree as different nodes.
