Difference between revisions of "Escaped identifiers in RTL files and in Verific data structures"
From Verific Design Automation FAQ
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'foo' is the same object as '\foo ' | 'foo' is the same object as '\foo ' | ||
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| + | The escaping characters '\' and ' ' are not part of the name! | ||
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| + | So, with AddSignal() when you define the name, you don't need to escape it. | ||
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| + | But when you refer to an escaped id, you need to escape it. | ||
'''VHDL: | '''VHDL: | ||
Revision as of 10:19, 16 March 2021
>>> This page is under construction <<<
Verific data structures: No escaped identifier
In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language format.
Verilog: starts with a backslash and ends with a space character
'foo' is the same object as '\foo '
The escaping characters '\' and ' ' are not part of the name!
So, with AddSignal() when you define the name, you don't need to escape it.
But when you refer to an escaped id, you need to escape it.
VHDL: enclosed in a pair backslashes
'\foo\' and 'foo' are too different objects
