Difference between revisions of "Escaped identifiers in RTL files and in Verific data structures"
From Verific Design Automation FAQ
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The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo ' | The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo ' | ||
| − | + | With AddSignal() when you define the name, you don't need to escape it. | |
But when you refer to an escaped id, you need to escape it. | But when you refer to an escaped id, you need to escape it. | ||
Revision as of 14:57, 16 March 2021
>>> This page is under construction <<<
Verific data structures:
No escaped identifier
In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language format.
Verilog:
starts with a backslash and ends with a space character
The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo '
With AddSignal() when you define the name, you don't need to escape it.
But when you refer to an escaped id, you need to escape it.
VHDL:
enclosed in a pair backslashes. The backslashes are part of the name.
'\foo\' and 'foo' are too different objects
