Difference between revisions of "Escaped identifiers in RTL files and in Verific data structures"
From Verific Design Automation FAQ
| Line 3: | Line 3: | ||
'''Verific data structures:''' | '''Verific data structures:''' | ||
| − | No | + | No naming rules, thus no need to escape identifiers. |
In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file. | In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file. | ||
| Line 9: | Line 9: | ||
'''Verilog:''' | '''Verilog:''' | ||
| − | + | Escaped identifiers start with a backslash and end with a space character. | |
The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo ' | The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo ' | ||
| Line 19: | Line 19: | ||
'''VHDL:''' | '''VHDL:''' | ||
| − | enclosed in a pair backslashes. The backslashes are part of the name. | + | Escaped identifiers are enclosed in a pair backslashes. The backslashes are part of the name. |
'\foo\' and 'foo' are too different objects | '\foo\' and 'foo' are too different objects | ||
Revision as of 17:57, 16 March 2021
>>> This page is under construction <<<
Verific data structures:
No naming rules, thus no need to escape identifiers.
In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file.
Verilog:
Escaped identifiers start with a backslash and end with a space character.
The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo '
With AddSignal() when you define the name, you don't need to escape it.
But when you refer to an escaped id, you need to escape it.
VHDL:
Escaped identifiers are enclosed in a pair backslashes. The backslashes are part of the name.
'\foo\' and 'foo' are too different objects
