Difference between revisions of "Escaped identifiers in RTL files and in Verific data structures"

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'''>>> This page is under construction <<<'''
 
'''>>> This page is under construction <<<'''
  
'''Verific data structures:'''
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'''Verific Data Structures :'''
  
No naming rules, thus no need to escape identifiers.
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There are no naming rules, hence no need to escape identifiers.
  
 
In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file.
 
In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file.
  
'''Verilog:'''
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'''Verilog :'''
  
Escaped identifiers start with a backslash and end with a space character.
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Escaped identifiers begin with a backslash and end with a space character.
  
The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo '
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The escaping characters '\' and ' ' are not part of the name 'foo' is the same object as '\foo '.
  
With AddSignal() when you define the name, you don't need to escape it.
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When using AddSignal() to create a new signal, the specified name does not need to be escaped.
  
But when you refer to an escaped id, you need to escape it.
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When referring to an escaped identifier, the name must be escaped.
  
To get 'Verilog name' for an identifier in the Verilog parsetree: VeriNode::MakeVerilogName()
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To get the 'Verilog name' for an identifier in the Verilog parsetree use VeriNode::MakeVerilogName()
  
To get 'Verilog name' for an identifier in the netlist database: VeriWrite::MakeVerilogName()
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To get the 'Verilog name' for an identifier in the netlist database use VeriWrite::MakeVerilogName()
  
'''VHDL:'''
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'''VHDL :'''
  
Escaped identifiers are enclosed in a pair backslashes. The backslashes are part of the name.
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Escaped identifiers are enclosed in a pair of backslashes.
 
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'\foo\' and 'foo' are too different objects
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The backslashes are part of the name '\foo\' and 'foo' are two different objects.

Revision as of 19:03, 16 March 2021

>>> This page is under construction <<<

Verific Data Structures :

There are no naming rules, hence no need to escape identifiers.

In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file.

Verilog :

Escaped identifiers begin with a backslash and end with a space character.

The escaping characters '\' and ' ' are not part of the name : 'foo' is the same object as '\foo '.

When using AddSignal() to create a new signal, the specified name does not need to be escaped.

When referring to an escaped identifier, the name must be escaped.

To get the 'Verilog name' for an identifier in the Verilog parsetree use VeriNode::MakeVerilogName()

To get the 'Verilog name' for an identifier in the netlist database use VeriWrite::MakeVerilogName()

VHDL :

Escaped identifiers are enclosed in a pair of backslashes.

The backslashes are part of the name : '\foo\' and 'foo' are two different objects.