Escaped identifiers in RTL files and in Verific data structures

>>> This page is under construction <<<

Verific data structures: No escaped identifier

In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language format.

Verilog: starts with a backslash and ends with a space character

'foo' is the same object as '\foo '

VHDL: enclosed in a pair backslashes

'\foo\' and 'foo' are too different objects