Escaped identifiers in RTL files and in Verific data structures

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Verific data structures:

No naming rules, thus no need to escape identifiers.

In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file.

Verilog:

Escaped identifiers start with a backslash and end with a space character.

The escaping characters '\' and ' ' are not part of the name. 'foo' is the same object as '\foo '

With AddSignal() when you define the name, you don't need to escape it.

But when you refer to an escaped id, you need to escape it.

To get 'Verilog name' for an identifier in the Verilog parsetree: VeriNode::MakeVerilogName()

To get 'Verilog name' for an identifier in the netlist database: VeriWrite::MakeVerilogName()

VHDL:

Escaped identifiers are enclosed in a pair backslashes. The backslashes are part of the name.

'\foo\' and 'foo' are too different objects