Escaped identifiers in RTL files and in Verific data structures

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Verific Data Structures :

There are no naming rules, hence no need to escape identifiers.

In netlist outputs and in pretty-print outputs, identifiers are escaped based on the naming rules of the language of the output file.

Verilog :

Escaped identifiers begin with a backslash and end with a space character.

The escaping characters '\' and ' ' are not part of the name : 'foo' is the same object as '\foo '.

When using AddSignal() to create a new signal, the specified name does not need to be escaped.

When referring to an escaped identifier, the name must be escaped.

To get the 'Verilog name' for an identifier in the Verilog parsetree use VeriNode::MakeVerilogName()

To get the 'Verilog name' for an identifier in the netlist database use VeriWrite::MakeVerilogName()

VHDL :

Escaped identifiers are enclosed in a pair of backslashes.

The backslashes are part of the name : '\foo\' and 'foo' are two different objects.