How to create a Netlist database from scratch (not from RTL input)

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A Perl example:

use strict;

push (@INC,"../../../extra_tests/pm");
require "";

# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
my $libset = Verific::Libset::Global();

# Add new library.  If RTL elaboration has been run, a library has been created
# already.  The default library is "work".
my $lib = Verific::Library->new("mylib");

# Add cell to the library.  In the Verilog netlist output, the cell name is the
# same as the module name.
my $cell = Verific::Cell->new("mycell");

# Add netlist to cell.  In the Verilog netlist output, the netlist name doesn't matter.
my $netlist = Verific::Netlist->new("mynetlist");

# Add ports to netlist
my $inport = Verific::Port->new("in", $Verific::DIR_IN);
my $outport = Verific::Port->new("out", $Verific::DIR_OUT);

# Add nets (Verilog: wire) to netlist
my $net1 = Verific::Net->new("in");

my $net2 = Verific::Net->new("out");

my $net3 = Verific::Net->new("n1");

# Add new library
my $primlib = Verific::Library->new("myprimitives");
# Create primitive inv
my $invcell = Verific::Cell->new("inv");
my $invnetlist = Verific::Netlist->new("primitive");
my $Ainport = Verific::Port->new("A", $Verific::DIR_IN);
my $Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT);
# Create primitive buff
my $buffcell = Verific::Cell->new("buff");
my $buffnetlist = Verific::Netlist->new("primitive");
$Ainport = Verific::Port->new("A", $Verific::DIR_IN);
$Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT);

# Instantiate inv in mynetlist
my $inst = $netlist->Add(Verific::Instance->new("inv1", $invnetlist));
if ($inst) {
    my $port = $invnetlist->GetPort("A");
    if ($port) {$net1->Connect($inst, $port);}
    $port = $invnetlist->GetPort("Z");
    if ($port) {$net3->Connect($inst, $port);}

# Instantiate buff in mynetlist
$inst = $netlist->Add(Verific::Instance->new("buff2", $buffnetlist));
if ($inst) {
    my $port = $buffnetlist->GetPort("A");
    if ($port) {$net3->Connect($inst, $port);}
    $port = $buffnetlist->GetPort("Z");
    if ($port) {$net2->Connect($inst, $port);}

# write netlist
my $veriWriter = Verific::VeriWrite->new();
$veriWriter->WriteFile(sprintf("%s.v",$netlist->Owner->Name()), $netlist);


# moved this to a subroutine to keep above code clean,
# this subroutine shows how to resolve linefile information
sub vfcprintf {
   my ($format) = (@_[0]);
   my ($lf) = (@_[1]);
   my @PARAMS;
   for (my $i = 2; $i < scalar(@_); $i++) {
   my $lf_format = ""; 
   if (Verific::LineFile::GetFileName($lf) && Verific::LineFile::GetLineNo($lf)) {
       my $lf_format = sprintf("%s(%s)",Verific::LineFile::GetFileName($lf), Verific::LineFile::GetLineNo($lf));
       printf "%s: $format\n",$lf_format,@PARAMS;
   } else {
       printf "$format\n",@PARAMS;

   return 0;