How to get all Verilog files being analyzed

Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?

Use this code:

Array *GetAllAbsFileNames() {
  Array *files = new Array() ;
  unsigned file_id = 1 ;
  const char *file_name ;
  while ((file_name=LineFile::GetAbsFileNameFromId(file_id++))!=0) {
    // Instead of LineFile::GetAbsFileNameFromId(), the API LineFile::GetFileNameFromId()
    // can also be used if relative file name is required.
    // This is a file we processed:
    files->Insert(file_name) ;
  }
  // Now analyzed_files array should contain names of all the files analyzed
  if (!file->Size()) { delete files ; files = 0 ; }
  return files ;
}

How this works:

1. Verific keeps file_name vs. file_id mapping.
2. File_id starts from 1 and increases by 1.
3. LineFile::GetFileNameFromId() returns 0 for non-existing id.
4. The code keeps calling the API with increnemted file_id until getting a 0.