Difference between revisions of "How to get best support from Verific"

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* Be clear and precise about the issue. Send us the log file if available; if not, a description of the symptom and the exact error/warning messages will help tremendously.<br />If it is at all possible, send us a testcase that we can use to re-create the symptom. If there is a problem, that testcase can be used to verify that the problem has been fixed. By the way, the testcase you provide will be added to the regression testsuite for your code branch. It will not be shared with anyone/organization outside of Verific.<br />The testcase should include Verilog/VHDL files, a TCL/Perl/Python script, or a C++ application exhibiting the symptom (current output), and the expected output.<br />''In sending the testcase, do not send screenshots. Rather, please send text files, or put them in the body of the email message so that we can save the files or cut and paste the text to create the testcase on our file system. If you send screenshots, we will have to type the files in, which takes time and is error-prone.''
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* Be clear and precise about the issue. Send us the log file if available; if not, a description of the symptom and the exact error/warning messages will help tremendously.<br />If it is at all possible, send us a testcase that we can use to re-create the symptom. If there is a problem, that testcase can be used to verify that the problem has been fixed. By the way, the testcase you provide will be added to the regression testsuite for your code branch. It will not be shared with anyone/organization outside of Verific.<br />The testcase should include Verilog/VHDL files, a TCL/Perl/Python script, or a C++ application exhibiting the symptom (current output), and the expected output.<br />''In sending the testcase, '''do not send screenshots'''. Rather, please send text files, or put them in the body of the email message so that we can save the files or cut and paste the text to create the testcase on our file system. If you send screenshots, we will have to type the files in, which takes time and is error-prone.''
  
 
* If you send a log file, please do not suppress any messages from Verific; they are essential in debugging. <br />To clear message suppressions, please use Message::ClearAllMessageTypes().
 
* If you send a log file, please do not suppress any messages from Verific; they are essential in debugging. <br />To clear message suppressions, please use Message::ClearAllMessageTypes().

Revision as of 21:37, 24 February 2021

We here at Verific strive to provide you with the best customer service.

But we need help from you. Please:

  • Identify your company and your group/business unit. Many of our customers have multiple Verific licenses, each with a different product configuration.
    On our file system, each of the licensees has a dedicated code branch, and code cross-contamination is an absolute no-no. Identifying your company and your business unit will help us to use the appropriate code branch.
    Another way is to tell us the name/email address of the person in your company that frequently deal with Verific.
  • Tell us what Verific release you are using:
    The API "Message::ReleaseString()" returns something like "Jul17_SW_Release."
    Or you can just search for "ReleaseString" in util/Message.cpp.
    Or you can run tclmain application with "-v" option:
   $ tclmain-linux-O -v
    -- (c) Copyright 1999 - 2020 Verific Design Automation Inc. All rights reserved
    -- Verific release: Mar20_SW_Release, to: Company, release date: Tue Apr 28 09:13:38 2020
    Hello, init.tcl has been executed
    %
  • Be clear and precise about the issue. Send us the log file if available; if not, a description of the symptom and the exact error/warning messages will help tremendously.
    If it is at all possible, send us a testcase that we can use to re-create the symptom. If there is a problem, that testcase can be used to verify that the problem has been fixed. By the way, the testcase you provide will be added to the regression testsuite for your code branch. It will not be shared with anyone/organization outside of Verific.
    The testcase should include Verilog/VHDL files, a TCL/Perl/Python script, or a C++ application exhibiting the symptom (current output), and the expected output.
    In sending the testcase, do not send screenshots. Rather, please send text files, or put them in the body of the email message so that we can save the files or cut and paste the text to create the testcase on our file system. If you send screenshots, we will have to type the files in, which takes time and is error-prone.
  • If you send a log file, please do not suppress any messages from Verific; they are essential in debugging.
    To clear message suppressions, please use Message::ClearAllMessageTypes().
  • If any of the older releases of Verific has a different behavior, and you are reporting a regression, tell us what release(s) of Verific you are comparing to. This will save us some time checking the old releases.
  • If there are other EDA tools that run "correctly," provide the names and the versions of the tools and their "correct" output. Do not just say, "Other tools accept the design" (then we will need to ask you the names of the tools).
  • Send email to support@verific.com. If you want to send email to an individual Verific engineer, add support@verific.com to the cc list.
    This email address is monitored by multiple Verific engineers in different time zones, so you likely get a response faster. And if the Verific engineer you send email to happens to be out of the office, other engineers can assist you.
  • If the problem is resolved at your end, inform us so we can close the issue.

Thank you very much.