How to get parameters creation-time initial expression/value after Static Elaboration

To ensure the proper functionality of this example, please enable the `VERILOG_PRESERVE_CREATION_INIT_VALUE_OF_PARAMS` compile flag. This flag is necessary because it adds a field to VeriParamId that stores the design-specified initial value.

We cannot use GetInitialValue for this purpose, as its value is overwritten with the evaluated parameter value during Static Elaboration. However, the creation-time initial value added by the flag will remain unaffected by Static Elaboration.

C++:

#include <iostream>
#include "Map.h"            // Make class Map available
#include "veri_file.h"      // Make verilog reader available
#include "VeriModule.h"     // Definition of a VeriModule and VeriPrimitive
#include "VeriExpression.h" // Definition of a VeriExpression
#include "Array.h"          // Make class Array available
#include "VeriId.h"         // Definitions of all verilog identifier nodes

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif
class ExModuleVisit : public VeriVisitor
{
public :
    ExModuleVisit() {}
    virtual ~ExModuleVisit() {}

    virtual void VERI_VISIT(VeriModule, node) 
    {
        std::cout << "-- Processing module " << node.GetName() << std::endl ;
        VeriVisitor::VERI_VISIT_NODE(VeriModule, node) ;
    }
    virtual void VERI_VISIT(VeriParamId, node)
    {
        std::cout << "--    Param " << node.GetName() << std::endl ;
        VeriExpression *init_val = node.GetInitialValue() ;
        if (init_val) {
            std::cout << "--        Initial value :" ;
            init_val->PrettyPrint(std::cout, 0) ; std::cout << std::endl ;
        }
        VeriExpression *creation_val = node.GetCreationInitialValue() ;
        if (creation_val) {
            std::cout << "--        Creation initial value :" ;
            creation_val->PrettyPrint(std::cout, 0) ; std::cout << std::endl ;
        }
    }
} ;


int main(int argc, char **argv)
{
#ifndef VERILOG_PRESERVE_CREATION_INIT_VALUE_OF_PARAMS
    std::cout << "Compile flag 'VERILOG_PRESERVE_CREATION_INIT_VALUE_OF_PARAMS' needs to be enabled for this application.\n"; 
    return 1 ;
#endif

    const char *file_name = 0 ;
    if (argc>1) {
        file_name = argv[1] ; // Set the file name as specified by the user
    } else {
        file_name = "test.sv" ; // Set default file name
    }
   
    if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;
    
    // Return in case of failure.
    if (!veri_file::ElaborateStatic("top", "work", 0)) {
        return 4 ;
    }
    ExModuleVisit m_obj ;                
    VeriModule *mod ;
    MapIter mi ;
    FOREACH_VERILOG_MODULE(mi, mod) {
        if (!mod) continue ;
        std::cout << "\n-- Processing module " << mod->GetName() << std::endl ;
        mod->Accept(m_obj) ;
        std::cout << "--> Calling StaticEvaluateCreationInitValuesOfParams on " << mod->GetName() << std::endl ;
        mod->StaticEvaluateCreationInitValuesOfParams() ;
        mod->Accept(m_obj) ; 
        if (mod->ResetStaticEvaluatedCreationInitValuesOfParams()) {
            std::cout << "--> Successfully called ResetStaticEvaluatedCreationInitValuesOfParams on " << mod->GetName() << std::endl ;
            mod->Accept(m_obj) ; 
        }
    }
    return 0 ;
}
 

input test.sv:

module top ;
  parameter p1 = 3 ;
  parameter p2 = p1 + 3 ;
  parameter p3 = p2 + 4 ;

  foo #(p2) I1() ;
  foo #(p3) I2() ;
endmodule

module foo ;
   parameter p1 = 1 ;
   parameter p2 = p1 + 4 ;
endmodule


 

Output log:

-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(2): INFO: compiling module 'top' (VERI-1018)

-- Processing module top
-- Processing module top
--    Param p1
--        Initial value :3
--        Creation initial value :3
--    Param p2
--        Initial value :6
--        Creation initial value :(p1 + 3)
--    Param p3
--        Initial value :10
--        Creation initial value :(p2 + 4)
--> Calling StaticEvaluateCreationInitValuesOfParams on top
-- Processing module top
--    Param p1
--        Initial value :3
--        Creation initial value :3
--    Param p2
--        Initial value :6
--        Creation initial value :6
--    Param p3
--        Initial value :10
--        Creation initial value :10

-- Processing module foo
-- Processing module foo
--    Param p1
--        Initial value :1
--        Creation initial value :1
--    Param p2
--        Initial value :(p1 + 4)
--        Creation initial value :(p1 + 4)
--> Calling StaticEvaluateCreationInitValuesOfParams on foo
-- Processing module foo
--    Param p1
--        Initial value :1
--        Creation initial value :1
--    Param p2
--        Initial value :(p1 + 4)
--        Creation initial value :5
--> Successfully called ResetStaticEvaluatedCreationInitValuesOfParams on foo
-- Processing module foo
--    Param p1
--        Initial value :1
--        Creation initial value :1
--    Param p2
--        Initial value :(p1 + 4)
--        Creation initial value :(p1 + 4)

-- Processing module foo(p1=6)
-- Processing module foo(p1=6)
--    Param p1
--        Initial value :6
--        Creation initial value :1
--    Param p2
--        Initial value :10
--        Creation initial value :(p1 + 4)
--> Calling StaticEvaluateCreationInitValuesOfParams on foo(p1=6)
-- Processing module foo(p1=6)
--    Param p1
--        Initial value :6
--        Creation initial value :1
--    Param p2
--        Initial value :10
--        Creation initial value :5

-- Processing module foo(p1=10)
-- Processing module foo(p1=10)
--    Param p1
--        Initial value :10
--        Creation initial value :1
--    Param p2
--        Initial value :14
--        Creation initial value :(p1 + 4)
--> Calling StaticEvaluateCreationInitValuesOfParams on foo(p1=10)
-- Processing module foo(p1=10)
--    Param p1
--        Initial value :10
--        Creation initial value :1
--    Param p2
--        Initial value :14
--        Creation initial value :5