How to ignore parameters/generics in elaboration

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Q:Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?

Specific parameters/generics of specific modules/units can be ignored during elaboration. Related APIs are:

   vhdl_file::GetIgnoreGeneric()
   vhdl_file::SetIgnoreGeneric()
   vhdl_file::RemoveAllIgnoreGeneric()
   veri_file::GetIgnoreParameter()
   veri_file::SetIgnoreParameter()
   veri_file::RemoveAllIgnoreParameter()

Below is an example as how to ignore all parameters in a library:

    veri_file::AnalyzeMultipleFiles(veri_files, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU);

    /*** Go through library "work" in the parsetree,
         find all parameters,
         and set "ignored" on all of them.
         Or you can select the paremeters to ignore ***/
    MapIter mi;
    VeriModule *module ;
    VeriLibrary *work_lib = veri_file::GetLibrary("work", 1);

    FOREACH_VERILOG_MODULE_IN_LIBRARY (work_lib, mi, module) { // do this for each module
        if (!module) continue;
        Array *parameters = module->GetParameters(); // collect all parameters
        if (!parameters) continue;
        unsigned i;
        VeriIdDef *param_id;
        FOREACH_ARRAY_ITEM(parameters, i, param_id) { // do this for each parameter of the module
            if (!param_id) continue;
            veri_file::SetIgnoreParameter(work_lib->GetName(), module->Name(), param_id->Name());
        }
    }
    
    if (!veri_file::Elaborate("top", "work", 0)) {
        return 1 ;
    }