https://www.verific.com/faq/index.php?title=How_to_traverse_scope_hierarchy&feed=atom&action=history
How to traverse scope hierarchy - Revision history
2024-03-28T18:34:01Z
Revision history for this page on the wiki
MediaWiki 1.26.3
https://www.verific.com/faq/index.php?title=How_to_traverse_scope_hierarchy&diff=746&oldid=prev
Hoa at 21:45, 26 October 2021
2021-10-26T21:45:38Z
<p></p>
<table class='diff diff-contentalign-left'>
<col class='diff-marker' />
<col class='diff-content' />
<col class='diff-marker' />
<col class='diff-content' />
<tr style='vertical-align: top;' lang='en'>
<td colspan='2' style="background-color: white; color:black; text-align: center;">← Older revision</td>
<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 21:45, 26 October 2021</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l69" >Line 69:</td>
<td colspan="2" class="diff-lineno">Line 69:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>     files.InsertLast("test.sv") ;</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>     files.InsertLast("test.sv") ;</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>     if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>     if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;</div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;"></ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">    // need to run static elaboration if any interface/module is parameterized</ins></div></td></tr>
<tr><td colspan="2"> </td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div><ins style="font-weight: bold; text-decoration: none;">    if (!veri_file::ElaborateAllStatic()) return 1 ;</ins></div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>     MapIter mi ;</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>     MapIter mi ;</div></td></tr>
</table>
Hoa
https://www.verific.com/faq/index.php?title=How_to_traverse_scope_hierarchy&diff=602&oldid=prev
Hoa: Created page with "C++ code: <nowiki> #include <iostream> #include <cstring> // strchr #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriConstVal.h" #inc..."
2021-02-01T21:02:52Z
<p>Created page with "C++ code: <nowiki> #include <iostream> #include <cstring> // strchr #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriConstVal.h" #inc..."</p>
<p><b>New page</b></p><div>C++ code:<br />
<br />
<nowiki><br />
#include <iostream><br />
#include <cstring> // strchr<br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriExpression.h"<br />
#include "VeriConstVal.h"<br />
#include "VeriScope.h"<br />
#include "Array.h"<br />
#include "Map.h"<br />
#include "Set.h"<br />
#include "VeriId.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
void PrintScopeHierarchy(VeriScope *scope, unsigned depth)<br />
{<br />
if (!scope) return ;<br />
char *prefix = 0 ;<br />
if (depth) {<br />
prefix = Strings::allocate(depth*4 +3) ;<br />
unsigned i ;<br />
for (i = 0; i < (depth *4); i++) prefix[i] = ' ' ;<br />
prefix[i] = 0 ;<br />
}<br />
VeriIdDef *owner = scope->GetOwner() ;<br />
VeriScope *upper = scope->Upper() ;<br />
Map *declared_ids = scope->DeclArea() ;<br />
MapIter mi ;<br />
char *name ;<br />
char *ids = 0 ;<br />
FOREACH_MAP_ITEM(declared_ids, mi, &name, 0) {<br />
const char *first_space = std::strchr(name, ' ') ;<br />
if (first_space && Strings::compare(first_space, name)) continue ;<br />
<br />
if (!ids) {<br />
ids = Strings::save(name) ;<br />
} else {<br />
char *tmp = ids ;<br />
ids = Strings::save(ids, ", ", name) ;<br />
Strings::free(tmp) ;<br />
}<br />
}<br />
if (upper) {<br />
(void) Message::Msg(VERIFIC_INFO, 0, 0, "%s |---Owner : %s : (defines : %s )",prefix ? prefix : "",<br />
owner ? owner->Name(): (scope->IsEmptyScope() ? "empty": "none"), ids) ;<br />
} else {<br />
(void) Message::Msg(VERIFIC_INFO, 0, 0, "Owner : %s : (defines : %s )",<br />
owner ? owner->Name(): (scope->IsEmptyScope() ? "empty": "none"), ids) ;<br />
}<br />
Strings::free(ids) ;<br />
Strings::free(prefix) ;<br />
<br />
Set *children = scope->GetChildrenScopes() ;<br />
SetIter si ;<br />
VeriScope *child ;<br />
FOREACH_SET_ITEM(children, si, &child) {<br />
PrintScopeHierarchy(child, depth+1) ;<br />
}<br />
}<br />
<br />
int main(int argc, char **argv)<br />
{<br />
Array files ;<br />
files.InsertLast("test.sv") ;<br />
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;<br />
<br />
MapIter mi ;<br />
VeriModule *module ;<br />
FOREACH_VERILOG_MODULE(mi, module) {<br />
if (!module) continue ;<br />
if (module->IsInterface()) continue ;<br />
<br />
PrintScopeHierarchy(module->GetScope(), 0) ;<br />
}<br />
<br />
return 0 ;<br />
}<br />
</nowiki><br />
Verilog testcase:<br />
<nowiki><br />
module array8(data_in, data_out);<br />
<br />
input [0:127] data_in;<br />
output [0:3] data_out;<br />
<br />
wire [7:0] arr[3:0][3:0]; // 2d array with word size 8<br />
wire [4:0] out_arr[3:0];<br />
genvar i, j;<br />
<br />
generate<br />
for (i = 0; i < 4; i = i + 1) begin : l1<br />
for (j = 0; j < 4; j = j + 1) begin : l2<br />
assign arr[i][j] = data_in[(4*i*8 + 8*j) +: 8];<br />
end<br />
end<br />
endgenerate<br />
<br />
generate<br />
for (i = 0; i < 4; i = i + 1) begin : l3<br />
adder_4_4 I (arr[i][0][7 -: 4], arr[i][1][6:3],<br />
arr[i][2][3:0], arr[i][3][4 -: 4],<br />
out_arr[i]);<br />
assign data_out[i] = out_arr[i][4];<br />
end<br />
endgenerate<br />
endmodule<br />
<br />
module adder_4_4(in1, in2, in3, in4, out1);<br />
input [3:0] in1;<br />
input [3:0] in2;<br />
input [3:0] in3;<br />
input [3:0] in4;<br />
output [4:0] out1;<br />
reg [4:0] out1;<br />
<br />
always@(in1, in2, in3, in4)<br />
begin<br />
out1 = in1 + in2 + in3 + in4;<br />
end<br />
endmodule<br />
</nowiki><br />
Run:<br />
<nowiki><br />
$ test-linux<br />
-- Analyzing Verilog file 'test.sv' (VERI-1482)<br />
INFO: Owner : array8 : (defines : data_in, data_out, arr, out_arr, i, j, l1, l3 )<br />
INFO: |---Owner : empty : (defines : (null) )<br />
INFO: |---Owner : l1 : (defines : i, l2 )<br />
INFO: |---Owner : empty : (defines : (null) )<br />
INFO: |---Owner : l2 : (defines : j )<br />
INFO: |---Owner : empty : (defines : (null) )<br />
INFO: |---Owner : l3 : (defines : i, I )<br />
INFO: Owner : adder_4_4 : (defines : in1, in2, in3, in4, out1 )<br />
INFO: |---Owner : empty : (defines : (null) )<br />
$<br />
</nowiki></div>
Hoa