Difference between revisions of "Instance - Module binding order"
From Verific Design Automation FAQ
| Line 5: | Line 5: | ||
# While parsing: | # While parsing: | ||
## `uselib | ## `uselib | ||
| + | ## -work (present working library) | ||
## -L | ## -L | ||
| − | |||
## -y/-v | ## -y/-v | ||
# While elaborating: | # While elaborating: | ||
## configurations | ## configurations | ||
## already resolved module from analysis, ie, order of parsing (above) | ## already resolved module from analysis, ie, order of parsing (above) | ||
Revision as of 11:26, 21 February 2023
Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?
The order of searching for modules is:
- While parsing:
- `uselib
- -work (present working library)
- -L
- -y/-v
- While elaborating:
- configurations
- already resolved module from analysis, ie, order of parsing (above)
