Difference between revisions of "Macro Callback example"

Latest revision as of 13:03, 6 May 2020

C++:

#include <iostream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"

#include "Strings.h"
#include "LineFile.h"
#include "Message.h"
#include "TextBasedDesignMod.h"

#include "Array.h"
#include "Map.h"
#include "Set.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyMacroCallBack : public MacroCallBackHandler
{
public:
    MyMacroCallBack() : MacroCallBackHandler(), _last_active_line(0), _last_inactive_line(0) { } 
    virtual ~MyMacroCallBack() { ReportInactiveArea() ; } 

public:
    void ReportInactiveArea()
    {   
        if (!_last_active_line || !_last_inactive_line || (_last_active_line > _last_inactive_line)) return ;

        Message::Msg(VERIFIC_INFO, 0, 0, "Inactive area [%d-%d]", _last_active_line, _last_inactive_line) ;

        _last_active_line = 0 ; 
        _last_active_line = 0 ; 
    }   

    virtual void PredefinedMacroRef(const char *macro_name, unsigned from_active_area, const linefile_type lf) 
    {   
        //Message::Msg(VERIFIC_INFO, 0, lf, "Macro %s is being referenced from %s area", macro_name, ((from_active_area)?"ACTIVE":"INACTIVE")) ;
        if (from_active_area) {
            if (_last_inactive_line) ReportInactiveArea() ;
            _last_active_line = LineFile::GetLineNo(lf) ; 
        } else if (_last_active_line) {
            _last_inactive_line = LineFile::GetLineNo(lf) ;
        }
    }

protected:
    unsigned _last_active_line ;
    unsigned _last_inactive_line ;
} ;

int main(int argc, const char **argv)
{
    MyMacroCallBack mc ;
    veri_file::RegisterCallBackMacro(&mc) ;

    veri_file::DefineCmdLineMacro("FORCE_STR") ;

    Array files(1) ;
    files.Insert("test.v") ;
    if (!veri_file::AnalyzeMultipleFiles(&files)) return 1 ;

    return 0 ;
}
 

Input Verilog:

module test (in, sel, clk, out);
    input [1:0] in;
    input clk,sel;
    output [1:0] out;

`ifdef FORCE_STR
    reg [1:0] a0;
    reg [1:0] a1;
    always @(posedge clk)
    begin
        a0 <= in+1;
        a1 <= in-1;
    end
    assign out = sel?a0:a1;

`else
    reg [1:0] b0;
    reg [1:0] b1;
    always @(posedge clk)
    begin
        b0 <= in+2;
        b1 <= in-2;
    end
    assign out = sel?b0:b1;

`endif

`ifndef FORCE_STR



`else



`endif

endmodule 
 

Run:

-- Analyzing Verilog file 'test.v' (VERI-1482)
INFO: Inactive area [16-26]
INFO: Inactive area [28-32]