Difference between revisions of "Main Page"

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* [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]]
 
* [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]]
 
* [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]]
 
* [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]]
 
 
 
 
  
  
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'''TCL, Perl, Python, Java'''
 
'''TCL, Perl, Python, Java'''
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''Number of views'' {{NUMBEROFVIEWS}}

Revision as of 17:25, 8 July 2016

General


VHDL, Verilog, Liberty, EDIF


Output

TCL, Perl, Python, Java

Number of views Template:NUMBEROFVIEWS