Difference between revisions of "Main Page"

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* [[What are the data | What are the data structures in Verific?]]
 
* [[What are the data | What are the data structures in Verific?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR | Does Verific support cross module references (XMR)?]]
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* [[Does Verific support cross| Does Verific support cross module references (XMR)?]]
  
  

Revision as of 13:01, 22 July 2016

General


VHDL, Verilog, Liberty, EDIF


Output

TCL, Perl, Python, Java