Difference between revisions of "Main Page"
From Verific Design Automation FAQ
| Line 12: | Line 12: | ||
* [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]] | * [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]] | ||
* [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]] | * [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]] | ||
| − | + | * [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]] | |
'''Output''' | '''Output''' | ||
'''TCL, Perl, Python, Java''' | '''TCL, Perl, Python, Java''' | ||
Revision as of 13:04, 22 July 2016
General
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
VHDL, Verilog, Liberty, EDIF
- I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?
- Why are the ports in original Verilog file renamed to p1, p2, ....?
- I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?
- A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?
- From the Verilog parsetree, how can I get the ports of a module?
Output
TCL, Perl, Python, Java
