Difference between revisions of "Main Page"

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'''General'''
 
'''General'''
 
* [[How do I know | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[How do I know | How do I know what language a Netlist in the netlist database comes from?]]
* [[What are the data | What are the data structures in Verific?]]
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* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific support cross| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support cross| Does Verific support cross module references (XMR)?]]

Revision as of 15:36, 22 July 2016

General


VHDL, Verilog, Liberty, EDIF

Output

TCL, Perl, Python, Java