Difference between revisions of "Main Page"

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* [[Design with VHDL-1993 and VHDL-2008 files | VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]]
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'''Output'''
 
'''Output'''
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'''TCL, Perl, Python, Java'''
 
'''TCL, Perl, Python, Java'''
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* [[What language can I use Verific software with? | What programming language can I use Verific software with??]]

Revision as of 16:54, 22 July 2016

General


VHDL, Verilog, Liberty, EDIF


Output


TCL, Perl, Python, Java