Difference between revisions of "Main Page"

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'''Output'''
 
'''Output'''
 
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* [[Output file formats | What languages does Verilog support?]]
  
 
'''TCL, Perl, Python, Java'''
 
'''TCL, Perl, Python, Java'''
 
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]
 
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

Revision as of 18:29, 22 July 2016

General


VHDL, Verilog, Liberty, EDIF


Output

TCL, Perl, Python, Java