Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
m
Line 11: Line 11:
 
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
 
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 +
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
 
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
 
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]

Revision as of 15:43, 26 October 2016

General

VHDL, Verilog (and System Verilog), Liberty, EDIF

Output

TCL, Perl, Python, Java