Difference between revisions of "Main Page"

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(Undo revision 273 by Michiel (talk))
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'''TCL, Perl, Python, Java'''
 
'''TCL, Perl, Python, Java'''
* [[What languages can I use with the Verific software? | What programming languages can I use with Verific software?]]
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* [[What languages can I use with the Verific software? | What programming languages can I use with the Verific software?]]

Revision as of 18:51, 11 January 2017

General

VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Output

TCL, Perl, Python, Java