Difference between revisions of "Main Page"

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* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 +
* [[How to get enums from Verilog parsetree | Verilog: From the parsetree, how can I get the enums declared in a module?]]
 
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
 
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
 
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
 
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]

Revision as of 10:32, 14 June 2017

General

VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Output

TCL, Perl, Python, Java