Difference between revisions of "Main Page"

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* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
 
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
 
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
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* [[Release version | How do I tell the version of a Verific software release? ]]
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* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
  
'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
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'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
 
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
 
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
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* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
 
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[How to identify packages being  imported into a module | Verilog: How to I identify packages being imported into a module?]]
 
 
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
 
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
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* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file?]]
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* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
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* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
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* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
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* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
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* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
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* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
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* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
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'''Netlist Database'''
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* [[How to create a Netlist database from scratch (not from RTL input) | A coding example as how to create Netlist database and its objects]]
  
 
'''Output'''
 
'''Output'''

Revision as of 17:13, 28 December 2018

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

TCL, Perl, Python, Java