Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 13: Line 13:
 
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
 
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
 
 
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
 
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
 
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
 
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
Line 30: Line 29:
 
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 +
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
 
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
 
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]

Revision as of 14:10, 28 February 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python