Difference between revisions of "Main Page"

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'''Code examples'''
 
'''Code examples'''
* [[Write out an encrypted netlist | Write out an encrypted netlist]]
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* [[Write out an encrypted netlist | Database: Write out an encrypted netlist]]
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* [[Extract clock enable | Database: Extract clock enable]]

Revision as of 14:04, 1 March 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples