Difference between revisions of "Main Page"

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* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
+
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
 
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
 
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
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* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 +
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++: Retrieve package name for user-defined variable types]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Revision as of 15:20, 7 March 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples