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* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
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* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
 
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
 
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
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* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
'''Netlist Database'''
 
'''Netlist Database'''
* [[How to create a Netlist database from scratch (not from RTL input) | A coding example as how to create Netlist database and its objects]]
 
  
 
'''Output'''
 
'''Output'''
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'''Code examples'''
 
'''Code examples'''
* [[Write out an encrypted netlist | Database: Write out an encrypted netlist]]
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* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Extract clock enable | Database: Extract clock enable]]
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* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog: Retrieve package name for user-defined variable types]]
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* [[Extract clock enable | Database/C++: Extract clock enable]]
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* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
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* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
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* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
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* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
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* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
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* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
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* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Revision as of 12:02, 9 April 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples