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'''General'''
 
'''General'''
* [[How to make lives easier | How to make lives easier]]
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* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
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* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
'''Netlist Database'''
 
'''Netlist Database'''
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* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
  
 
'''Output'''
 
'''Output'''
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* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
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* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
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* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
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* [[Type Range example | Verilog/C++: Type Range Example]]
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* [[Macro Callback example | Verilog/C++: Macro Callback example]]
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* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]
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*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Revision as of 14:07, 21 August 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples