Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
(3 intermediate revisions by the same user not shown)
Line 39: Line 39:
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
'''Netlist Database'''
 
'''Netlist Database'''
 +
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
  
 
'''Output'''
 
'''Output'''
Line 53: Line 54:
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 +
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 +
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
* [[Test-based design modification | Verilog/C++: Test-based design modification]]  
+
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  
 
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]

Revision as of 14:07, 21 August 2019

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples