Difference between revisions of "Main Page"
From Verific Design Automation FAQ
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'''General''' | '''General''' | ||
+ | * [[How to get best support from Verific | '''''How to get best support from Verific''''']] | ||
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]] | * [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]] | ||
* [[Verific data structures | What are the data structures in Verific?]] | * [[Verific data structures | What are the data structures in Verific?]] | ||
Line 5: | Line 6: | ||
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]] | * [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]] | ||
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]] | * [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]] | ||
− | * [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]] | + | * [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]] |
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]] | * [[Message handling | How do I downgrade/upgrade messages from Verific? ]] | ||
+ | * [[Release version | How do I tell the version of a Verific software release? ]] | ||
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | * [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | ||
− | '''VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' | + | '''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' |
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | * [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | ||
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | * [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | ||
− | |||
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]] | * [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]] | ||
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]] | * [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]] | ||
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | * [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | ||
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]] | * [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]] | ||
− | |||
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]] | * [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]] | ||
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]] | * [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]] | ||
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]] | * [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]] | ||
* [[How to find port dimensions | Verilog: How do I get port dimensions?]] | * [[How to find port dimensions | Verilog: How do I get port dimensions?]] | ||
− | |||
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]] | * [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]] | ||
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]] | * [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]] | ||
− | * [[SystemVerilog "std" package | | + | * [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]] |
+ | * [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]] | ||
+ | * [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]] | ||
+ | * [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]] | ||
+ | * [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]] | ||
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | * [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | ||
+ | * [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]] | ||
+ | * [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]] | ||
+ | * [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]] | ||
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]] | * [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]] | ||
+ | * [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]] | ||
+ | * [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]] | ||
+ | * [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]] | ||
+ | * [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]] | ||
+ | * [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]] | ||
+ | '''Netlist Database''' | ||
+ | * [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]] | ||
'''Output''' | '''Output''' | ||
* [[Output file formats | What language formats does Verific support as output?]] | * [[Output file formats | What language formats does Verific support as output?]] | ||
− | '''TCL, Perl, Python | + | '''Scripting languages: TCL, Perl, Python''' |
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]] | * [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]] | ||
+ | |||
+ | '''Code examples''' | ||
+ | * [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]] | ||
+ | * [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]] | ||
+ | * [[Extract clock enable | Database/C++: Extract clock enable]] | ||
+ | * [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]] | ||
+ | * [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]] | ||
+ | * [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]] | ||
+ | * [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]] | ||
+ | * [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]] | ||
+ | * [[Type Range example | Verilog/C++: Type Range Example]] | ||
+ | * [[Macro Callback example | Verilog/C++: Macro Callback example]] | ||
+ | * [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]] | ||
+ | *[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]] | ||
+ | * [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]] | ||
+ | * [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]] | ||
+ | * [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]] | ||
+ | * [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]] |
Revision as of 14:37, 4 October 2019
General
- How to get best support from Verific
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- How do I remove all Verific data structures in memory?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
- Are there options to control Verific software's behavior? Compile-time & run-time flags.
- How do I downgrade/upgrade messages from Verific?
- How do I tell the version of a Verific software release?
- How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"
Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF
- Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- Verilog: How do I get the list of included files associated with a Verilog source file?
- Verilog: How to get type/initial value of parameters.
- Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?
- Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- Verilog: From the Verilog parsetree, how can I get the ports of a module?
- Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?
- Verilog: How do I get the library that contains the module nested inside another module?
- Verilog: How do I get linefile information of macro definitions?
- Verilog: How do I get port dimensions?
- Verilog: What is the order of binding modules to instances?
- Verilog: Does Verific replace constant expressions with their respective values?
- SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?
- SystemVerilog: From the parsetree, how can I get the enums declared in a module?
- SystemVerilog: How do I identify packages being imported into a module?
- SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.
- SystemVerilog: Support for SystemVerilog top level module with interface ports.
- VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- Verilog/VHDL: How to prettyprint a parsetree node to a string.
- Verilog/VHDL: What does 'static elaboration' do?
- Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.
- Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?
- Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?
- Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?
- Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?
- Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?
- Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?
Netlist Database
Output
Scripting languages: TCL, Perl, Python
Code examples
- Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)
- Database/C++: Write out an encrypted netlist
- Database/C++: Extract clock enable
- Database/Verilog/C++: Process -f file and explore the Netlist Database
- Database/Verilog/Python: Process -f file and explore the Netlist Database
- Verilog/C++: Statically elaborate with different values of parameters
- Verilog/C++: Prettyprint all modules in the design hierarchy
- Verilog/C++: Getting instances' parameters
- Verilog/C++: Type Range Example
- Verilog/C++: Macro Callback example
- Verilog/C++: Comment out a line using test-based design modification and parsetree modification
- Verilog/Perl: Access attributes of ports in parsetree
- SystemVerilog/C++/Python: Retrieve package name for user-defined variable types
- SystemVerilog/C++: Pretty-print a module and the packages imported by the module
- SystemVerilog/C++: How to get packed dimensions of enum
- Verilog/VHDL/C++: Traverse instances in parsetree