Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 59: Line 59:
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range Example]]
+
* [[Type Range example (simple) | Verilog/C++: Type Range Example]]
 +
* [[Type Range example with multi-dimensional arrays| Verilog/C++: Type Range example with multi-dimensional arrays]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]

Revision as of 18:21, 22 January 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples