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'''Netlist Database'''
 
'''Netlist Database'''
 
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
 
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
 
+
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
 +
* [[System attributes | Netlist Database: System attributes]]
 
'''Output'''
 
'''Output'''
 
* [[Output file formats | What language formats does Verific support as output?]]
 
* [[Output file formats | What language formats does Verific support as output?]]
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* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Memory elements of a RamNet | Database/C++: Memory elements of a RamNet]]
+
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
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* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example (simple) | Verilog/C++: Type Range Example]]
+
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++: Type Range example with multi-dimensional arrays]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++: Type Range example with multi-dimensional arrays]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 +
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  

Revision as of 14:27, 13 February 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples