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'''General'''
 
'''General'''
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* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
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* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
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* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
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* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
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* [[Release version | How do I tell the version of a Verific software release? ]]
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* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
  
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'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
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* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
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* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
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* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
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* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
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* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
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* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
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* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
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* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
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* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
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* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
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* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
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* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
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* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
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* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
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* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
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* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
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* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
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* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
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* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
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* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
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* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
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* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
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* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
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* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
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* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
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* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
  
'''VHDL, Verilog, Liberty, EDIF'''
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* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
* [[I'm using -v, -y, | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
+
'''Netlist Database'''
* [[While looking at a Netlist | While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?]]
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* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Why are the ports | Why are the ports in original Verilog file renamed to p1, p2, ....?]]
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* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[ I have a design consisting of | I have a design consisting of a mixture of Verilog 2001 and SystemVerilog input files. Should I parse all the files as SystemVerilog?]]
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* [[System attributes | Netlist Database: System attributes]]
* [[ A customer wants to analyze/elaborate | A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE library set, do you have any suggestion on how to handle this scenario?]]
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* [[How to get module ports from Verilog parsetree | From the Verilog parsetree, how can I get the ports of a module?]]
+
  
 
'''Output'''
 
'''Output'''
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* [[Output file formats | What language formats does Verific support as output?]]
  
'''TCL, Perl, Python, Java'''
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'''Scripting languages: TCL, Perl, Python'''
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* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]
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'''Code examples'''
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* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
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* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
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* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
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* [[Extract clock enable | Database/C++: Extract clock enable]]
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* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
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* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
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* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
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* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
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* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
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* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
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* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
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* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
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* [[Type Range example with multi-dimensional arrays| Verilog/C++: Type Range example with multi-dimensional arrays]]
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* [[Macro Callback example | Verilog/C++: Macro Callback example]]
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* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
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* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
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* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
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* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
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* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
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* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
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* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
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* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
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* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Revision as of 13:25, 14 May 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples