Difference between revisions of "Main Page"

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* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
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* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]

Revision as of 17:29, 2 June 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples