Difference between revisions of "Main Page"

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* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
 
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
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* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Release version | How do I tell the version of a Verific software release? ]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
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'''Code examples'''
 
'''Code examples'''
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
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* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
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* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
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* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
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* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
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* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
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* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
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* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
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* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Revision as of 12:58, 23 June 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples