Difference between revisions of "Main Page"

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* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 +
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl: How to get linefile data of macros - Macro callback function]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl: How to get linefile data of macros - Macro callback function]]

Revision as of 13:54, 1 February 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples