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* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
 
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
 
* [[LineFile data from input files | LineFile data from input files]]
 
* [[LineFile data from input files | LineFile data from input files]]
 +
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
  
 
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
 
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
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* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
 
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
 
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
 +
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
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* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 +
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 +
* [[Simple example of visitor pattern | Verilog/C++: Simple example of visitor pattern]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
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* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++: Type Range example with multi-dimensional arrays]]
+
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
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* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 +
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 +
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 +
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl: How to get linefile data of macros - Macro callback function]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]

Revision as of 16:39, 22 February 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples