Difference between revisions of "Main Page"

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* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Simple example of visitor pattern | Verilog/C++: Simple example of visitor pattern]]
 
* [[Simple example of visitor pattern | Verilog/C++: Simple example of visitor pattern]]
* [[Where in RTL is it get assigned? | Verilog/C++: Where in RTL is it get assigned?]]
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* [[Where in RTL is it get assigned? | Verilog/C++: Where in RTL does it get assigned?]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]

Revision as of 13:56, 23 March 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples