Difference between revisions of "Main Page"

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* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text-based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
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* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]

Revision as of 14:16, 8 April 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples