Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
(18 intermediate revisions by 2 users not shown)
Line 1: Line 1:
 
'''General'''
 
'''General'''
 
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 +
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
 
* [[Verific data structures | What are the data structures in Verific?]]
Line 22: Line 23:
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
 
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
+
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
 
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
 
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
 
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
Line 34: Line 35:
 
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 +
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures '''(under construction)'''.]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
 
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
Line 62: Line 64:
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 +
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
 +
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 +
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple example of visitor pattern]]
+
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
 +
* [[Where in RTL does it get assigned? | Verilog/C++/Python/Perl: Where in RTL does it get assigned?]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
Line 73: Line 79:
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text-based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
+
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 +
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 +
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]

Revision as of 10:58, 21 April 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples