Difference between revisions of "Main Page"

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* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple example of visitor pattern]]
+
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
 
* [[Where in RTL does it get assigned? | Verilog/C++/Python/Perl: Where in RTL does it get assigned?]]
 
* [[Where in RTL does it get assigned? | Verilog/C++/Python/Perl: Where in RTL does it get assigned?]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]

Revision as of 10:58, 21 April 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples