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'''General'''
 
'''General'''
 
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
 +
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
 
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
 
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
 
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
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* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
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* [[Notes on analysis | SystemVerilog: Notes on analysis]]
 
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
 
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
 
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
 
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
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* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures '''(under construction)'''.]]
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* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
 
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
 
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
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* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
 
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
 
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string]]
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* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
  
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
 
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
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'''Code examples'''
 
'''Code examples'''
 
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
 
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
 
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Extract clock enable | Database/C++: Extract clock enable]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
 
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
 
 
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
 
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
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* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
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* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
 
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
 
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
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* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
 
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
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* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
 
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
 
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Where in RTL does it get assigned? | Verilog/C++/Python/Perl: Where in RTL does it get assigned?]]
 
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
 
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
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* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
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* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
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* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
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* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
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* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 +
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
 
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]

Revision as of 10:34, 15 October 2021

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples