Difference between revisions of "Main Page"

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* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 +
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
 
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  

Revision as of 08:49, 14 April 2022

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples