Difference between revisions of "Main Page"

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* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
 
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
 
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
 
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
 +
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]

Revision as of 11:00, 2 May 2022

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples