Difference between revisions of "Main Page"

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* [[LineFile data from input files | LineFile data from input files]]
 
* [[LineFile data from input files | LineFile data from input files]]
 
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
 
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving nets | Preserving user nets - preventing nets from being optimized away]]
+
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
  
 
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
 
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
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* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Type Range example | Verilog/C++: Type Range example  (simple)]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
 +
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
 
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]  
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* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
 
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
 
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
 
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
 +
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
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* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 +
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
 
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
 
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Revision as of 17:14, 12 May 2022

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples