Difference between revisions of "Main Page"

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* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
 
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
 
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with "_1", "_2", ..., suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
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* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
 
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
 
* [[Notes on analysis | SystemVerilog: Notes on analysis]]

Revision as of 15:11, 27 September 2022

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples