Difference between revisions of "Main Page"

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* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
 
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
 
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
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* [[Verilog ports being renamed | Verilog: Port Expressions]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
 
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
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* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
 
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
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* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]

Revision as of 13:50, 24 April 2023

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples